Currently, data processing systems such as personal computers include a system memory having a plurality of memory modules composed of DRAM modules. A common form of such modules is a single in-line memory module (SIMM) in which a plurality of DRAM chips are integrated into a single package. Many personal computers are built with a plurality of sockets into which the SIMMs can be plugged. In many cases, the sockets are not initially filled, but as the user's needs increase, additional SIMMs are added.
Each module is characterized by many factors such as size or memory capacity, speed, memory address organization or ratio of rows to columns, etc. A memory module also requires timing or control signals to be presented thereto in precisely timed manner in accordance with the timing requirements of the module. Such timing requirements include pulse widths, transition times, hold times, precharge times, etc. Although there are many different times associated with a DRAM, the speed thereof is normally expressed by the data access time from the falling edge of RAS. A DRAM is accessed by applying different actuating signals thereto in predefined sequences dependent on the type of memory function. A typical DRAM has terminals for receiving signals such as write enable (WE#), DATA in and out, multiplexed row address and column address, row address strobe (RAS), and column address strobe (CAS).
In a data processing system, access to memory is controlled by a memory controller. Memory controllers are typically designed to support a particular type of memory and run at a particular speed determined by the system clock or speed of a microprocessor. The memory controller hardware must be designed to accommodate the timing requirements of different speed DRAMs. In addition, as the operating frequency of the memory controller is increased, the hardware must change if the timing requirements of the DRAMs have been violated.
When a given system has room for adding memory modules, such modules generally have to run at the same speed or faster than the original modules for which the associated memory controller has been designed. When faster modules are added, the system still runs at the slower design speed so that the speed of the faster modules cannot be taken advantage of.